1. Field of the Invention
The present invention relates about a method for forming interconnect, more particularly using dual damascene for precisely controlling the shape and area of the interconnect.
2. Description of the Prior Art
Currently, demand for integrated circuit (I.C.) has rapidly increased due to widespread use of electronic equipment. In particular, the increasing popularity of some electronic equipment such as, for example, many kinds of computers are gradually increasing the demand for the large or very large semiconductor memories in this modern century and next coming twenty-one century. Therefore, the advanced manufacture technology for improvement fabrication of integrated circuit should be urgently need than before.
Normally, the size and performance of the power IC devices depends critically on a specific at a particular breakdown voltage of the output devices. Since the thickness of semiconductor is usually limited by technological constraints, higher breakdown voltages typically require more layers. However, since the device on resistance is proportional to the expitaxial layer resistivity, higher breakdown voltages have to generally be traded off for limited drive current capability.
Thus, there is a conventional method described as referring with FIG. 1A to 1D, which are the method for forming inter-metal dielectric by using dual damascene for precisely controlling the shape and area of the interconnect. Then, The following description will explain the various steps of one conventional method for forming dual damascene structure by reference FIG. 1.
In the manufacture of a conventional dual damascene structure, there a substrate 100 has a metal layer 120 formed therein as shown in FIG. 1A. An inter-metal dielectric layer 130 and a stop layer 132 are subsequently deposited on the substrate 100. This stop layer 132 is silicon nitride as a trench etching stop layer. Then, another inter-metal dielectric layer 134 is coated on the stop layer 132. A via patterned photoresist layer 140 is formed. Then, an anisotropically etch is performed to etch through inter-metal dielectric layer 134, stop layer 132, and inter-metal dielectric layer 130, as shown in FIG. 1B. Another photoresist layer 142 having a trench line pattern is formed next. Referring to FIG. 1C, trench line pattern 152 is transferred into the inter-metal dielectric layer 134 and ceased at stop layer 132. Then, the photoresist layer 142 is removed. A barrier layer 162 is deposited and a metal layer 160, such as tungsten or copper, is subsequently deposited to fill the via hole and trench line, as shown in FIG. 1D. Finally, the dual damascene structure is completed by using chemical mechanical polishing method to remove excess metal layer.
For 0.18 .mu.m process and beyond, dual damascene process is a key technology to push design rule tightly, but it is difficult to control the process window especially in via and metal trench formation. Thus, good resolution of lithography (misalignment issue) and high selectivity of via etching is the key issue for back end interconnection.
Therefore, within the microelectronics industry, there is an ongoing trend toward miniaturization coupled with higher performance. The scaling of transistors toward smaller dimensions, higher speeds, and low power has resulted in an urgent need for low constant inter-level insulators. Low dielectric constant inter-level dielectrics have already been identified as being critical to the realization of high performance integrated circuits. Thus, there exists a need in the microelectronics industry for a thermally stable, non-corrosive low dielectric constant polymer with good solvent resistance, high glass transition temperature, good mechanical performance and good adhesive properties, particularly to copper.